#include <RoutIntAddr.h>
RoutIntAddr::RoutIntAddr | ( | void | ) |
Clock_phase_fine_delay_selected = (areg =='hf3) --> write and read register with 2 bits with the follow format:
Error handler Global RESET (for all FSMs and SPM)
RoutIntAddr::~RoutIntAddr | ( | void | ) |
void RoutIntAddr::SetRoutBoardAddr | ( | UInt32 | BrdAdd | ) |
void RoutIntAddr::ShiftAddresses | ( | int | Nshift | ) |
void RoutIntAddr::ModifyRouterAddresses | ( | void | ) |
UInt32 RoutIntAddr::GetDPMBaseAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetSPMBaseAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetLinkRxBaseAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetRtFPGAVersion | ( | ) | [inline] |
UInt32 RoutIntAddr::GetCntrRegAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetStatusReg1Addr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetStatusReg2Addr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetStatusReg3Addr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetRtVMEResetAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetDigPilotResetAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetStatusRegJTAGSelAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetDataRegSelAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetRegSelAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetFeDDLStatusWordAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetResetDetectorAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetRdStartAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetRdLEnghtOfBlockAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetWtHistogramAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetRdHistogramAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetJPlayerAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetRdL0IdAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetRdL2aIdAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetResetBcntAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetIrqPushButtonAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetResetTempLimitAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetFOFromVMEAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetResetTTCrxAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetResetLinkRxAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetSendTriggSeqAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetDPMfifoStartAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetDPMfifoEndAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetFlushDPMAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetRdL1IdAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetRdFONumbAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetExtraHeaderFifoAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetResetExtraHeaderFifoAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetTimeL0L1 | ( | ) | [inline] |
UInt32 RoutIntAddr::GetFOGlobalCountAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetFOCoincedenceCountAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetFOTimeCountAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetResetPixelAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetLrxL1InFifo | ( | ) | [inline] |
UInt32 RoutIntAddr::GetRxReadyAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetResetBusyresolverAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetTimeBusyDaqAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetTimeBusyRouterAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetTimeBusyHsAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetTimeBusyTriggersL1FifoAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetNumTransBusyDaqAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetNumTransBusyRouterAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetNumTransBusyHsAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetNumTransBusyTriggersL1FifoAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetL0CounterAddr | ( | ) | [inline] |
UInt32 RoutIntAddr::GetErrorMask | ( | ) | [inline] |
UInt32 RoutIntAddr::GetInterlockStatus | ( | ) | [inline] |
UInt32 RoutIntAddr::GetClockPhaseFineDelay | ( | ) | [inline] |
UInt32 RoutIntAddr::GetErrManagerReset | ( | ) | [inline] |
UInt32 RoutIntAddr::GetTpL1Delay | ( | ) | [inline] |
UInt32 RoutIntAddr::BoardAddr [private] |
UInt32 RoutIntAddr::RoutDPMBaseAddr [private] |
UInt32 RoutIntAddr::RoutSPMBaseAddr [private] |
UInt32 RoutIntAddr::RoutLinkRxBaseAddr [private] |
UInt32 RoutIntAddr::RtFPGAVersion [private] |
UInt32 RoutIntAddr::CntrRegAddr [private] |
UInt32 RoutIntAddr::StatusReg1Addr [private] |
UInt32 RoutIntAddr::StatusReg2Addr [private] |
UInt32 RoutIntAddr::StatusReg3Addr [private] |
UInt32 RoutIntAddr::VMEResetAddr [private] |
UInt32 RoutIntAddr::DigPilotResetAddr [private] |
UInt32 RoutIntAddr::StatusRegJTAGSelAddr [private] |
UInt32 RoutIntAddr::DataRegSelAddr [private] |
UInt32 RoutIntAddr::RegSelAddr [private] |
UInt32 RoutIntAddr::FeDDLStatusWordAddr [private] |
UInt32 RoutIntAddr::ResetDetectorAddr [private] |
UInt32 RoutIntAddr::RdStartAddr [private] |
UInt32 RoutIntAddr::RdLEnghtOfBlockAddr [private] |
UInt32 RoutIntAddr::WtHistogramAddr [private] |
UInt32 RoutIntAddr::RdHistogramAddr [private] |
UInt32 RoutIntAddr::JPlayerAddr [private] |
UInt32 RoutIntAddr::RdL0IdAddr [private] |
UInt32 RoutIntAddr::RdL2aIdAddr [private] |
UInt32 RoutIntAddr::ResetBcntAddr [private] |
UInt32 RoutIntAddr::IrqPushButtonAddr [private] |
UInt32 RoutIntAddr::ResetTempLimitAddr [private] |
UInt32 RoutIntAddr::StatusRegLinkRxAddr[6][16] [private] |
UInt32 RoutIntAddr::FOFromVMEAddr [private] |
UInt32 RoutIntAddr::ResetTTCrxAddr [private] |
UInt32 RoutIntAddr::ResetLinkRxAddr [private] |
UInt32 RoutIntAddr::SendTriggSeqAddr [private] |
UInt32 RoutIntAddr::DPMfifoStartAddr [private] |
UInt32 RoutIntAddr::DPMfifoEndAddr [private] |
UInt32 RoutIntAddr::FlushDPMAddr [private] |
UInt32 RoutIntAddr::RdL1IdAddr [private] |
UInt32 RoutIntAddr::RdFONumbAddr [private] |
UInt32 RoutIntAddr::ExtraHeaderFifoAddr [private] |
UInt32 RoutIntAddr::ResetExtraHeaderFifoAddr [private] |
UInt32 RoutIntAddr::FOGlobalCountAddr [private] |
UInt32 RoutIntAddr::FOCoincedenceCountAddr [private] |
UInt32 RoutIntAddr::FOLinkRxCountAddr[3] [private] |
UInt32 RoutIntAddr::FOTimeCountAddr [private] |
UInt32 RoutIntAddr::ScopeSelectorAddr[3] [private] |
UInt32 RoutIntAddr::ResetHalfStaveAddr[6] [private] |
UInt32 RoutIntAddr::RdTempChAddr[6] [private] |
UInt32 RoutIntAddr::TempLimitMcmAddr[6] [private] |
UInt32 RoutIntAddr::TempLimitBusAddr[6] [private] |
UInt32 RoutIntAddr::JTResetStateMacAddr[7] [private] |
UInt32 RoutIntAddr::JTResetFIFOsAddr[7] [private] |
UInt32 RoutIntAddr::JTResetChAddr[7] [private] |
UInt32 RoutIntAddr::JTRdWrDataAddr[7] [private] |
UInt32 RoutIntAddr::JTExStartAddr[7] [private] |
UInt32 RoutIntAddr::JTStatusRegAddr[7] [private] |
UInt32 RoutIntAddr::JTRdEnFIFOin[7] [private] |
UInt32 RoutIntAddr::JTRdNumbFIFOin[7] [private] |
UInt32 RoutIntAddr::ResetPixelAddr [private] |
UInt32 RoutIntAddr::TimeL0L1 [private] |
UInt32 RoutIntAddr::LrxL1InFifo [private] |
memory adresses added by Michele
UInt32 RoutIntAddr::RxReady [private] |
UInt32 RoutIntAddr::ResetBusyresolver [private] |
UInt32 RoutIntAddr::TimeBusyDaq [private] |
UInt32 RoutIntAddr::TimeBusyRouter [private] |
UInt32 RoutIntAddr::TimeBusyHs [private] |
UInt32 RoutIntAddr::TimeBusyTriggersL1Fifo [private] |
UInt32 RoutIntAddr::NumTransBusyDaq [private] |
UInt32 RoutIntAddr::NumTransBusyRouter [private] |
UInt32 RoutIntAddr::NumTransBusyHs [private] |
UInt32 RoutIntAddr::L0Counter [private] |
UInt32 RoutIntAddr::RouterErrorMask [private] |
UInt32 RoutIntAddr::ReadInterlockStatus [private] |
Read_interlock_Status_selected = (areg =='hf4) --> only read, you received 7 bits with the following format: Router_Interlock Interlock on HS_5 Interlock on HS_4 Interlock on HS_3 Interlock on HS_2 Interlock on HS_1 Interlock on HS_0
UInt32 RoutIntAddr::ClockPhaseFineDelay [private] |
Clock_phase_fine_delay_selected = (areg =='hf3) --> write and read register with 2 bits with the follow format:.
UInt32 RoutIntAddr::ErrManagerReset [private] |
Error handler Global RESET (for all FSMs and SPM).
UInt32 RoutIntAddr::TpL1Delay [private] |
defines the L1 delay for the test pulse, like this we can have the same delay for calibration and real particles