F:/projectos/SpdFEDServerPackage/SpdFEDServerRelease/AddressGenerator/lrx_rt_reg_def.h File Reference

Defines
#define	RESET_EXTRA_HEADER_FIFO_ADDR   0x2F;
#define	RESET_BCNT_ADDR   0x2D;
#define	VME_RESET_ADDR   0x23;
#define	RESET_LINK_RX_ADDR   0x0f;
#define	RT_FPGA_VERSION   0x01;
#define	RESET_PIXEL_ADDR   0xE2;
#define	RD_FO_NUMBADDR   0x14;
#define	RD_LENGHT_OF_BLOCK_ADDR   0x0b;
#define	RD_START_ADDR   0x0a;
#define	STATUS_REG2_ADDR   0x04;
#define	FO_GLOBAL_COUNT_ADDR   0x6C;
#define	SEND_TRIGG_SEQ_ADDR   0x10;
#define	STATUS_REG3_ADDR   0x05;
#define	FO_TIME_COUNT_ADDR   0x71;
#define	RD_L2A_ID_ADDR   0x2C;
#define	FLUSH_DPM_ADDR   0x12;
#define	RESET_TTCRX_ADDR   0x0e;
#define	STATUS_REG1_ADDR   0x03;
#define	FO_FROM_VME_ADDR   0x7f;
#define	IRQ_PUSH_BUTTON_ADDR   0x2A;
#define	FO_COINCEDENCE_COUNT_ADDR   0x6D;
#define	RD_L0ID_ADDR   0x2B;
#define	J_PLAYER_ADDR   0x15;
#define	DPM_FIFO_START_ADDR   0x11;
#define	WT_HISTOGRAM_ADDR   0x0c;
#define	CNTR_REG_ADDR   0x02;
#define	RD_L1_ID_ADDR   0x13;
#define	RD_HISTOGRAM_ADDR   0x0d;
#define	EXTRA_HEADER_FIFO_ADDR   0x2E;
#define	FED_DL_STATUS_WORD_ADDR   0x07;
#define	RESET_TEMP_LIMIT_ADDR   0x76;
#define	DPM_FIFO_END_ADDR   0x22;
#define	DIG_PILOT_RESET_ADDR   0xE0;
#define	RESET_DETECTOR_ADDR   0x09;
#define	LRX_DATA_ENCODER_STATUS3_ADDR   0x400089;
#define	LRX_EN_MOVE_BIT_ADDR   0x400034;
#define	LRX_MCM_STIMULI_DATA   0x400017;
#define	LRX_DPM_ADDR_COUNT_ADDR   0x40000b;
#define	LRX_BUSY_MASK_ADDR   0x400012;
#define	LRX_TEMP_ADDR   0x400002;
#define	LRX_STATUS_REG_ADDR   0x400001;
#define	LRX_INPUT_STAGE_STATUS0_ADDR   0x400081;
#define	LRX_RESET_SOFT_ADDR   0x40000e;
#define	LRX_DATA_ENCODER_STATUS6_ADDR   0x40008C;
#define	LRX_FIFO_PIX_DATA_STATUS_ADDR   0x400084;
#define	LRX_EV_DESCR_RAM_STATUS_ADDR   0x400083;
#define	LRX_L1_MEM_START_ADDR   0x400060;
#define	LRX_BUSY_CONTROL_ADDR   0x400032;
#define	LRX_CNTR_REG_ADDR   0x400000;
#define	LRX_DATA_ENCODER_STATUS7_ADDR   0x40008D;
#define	LRX_DATA_ENCODER_STATUS0_ADDR   0x400086;
#define	LRX_EVENT_START_ADDR   0x400040;
#define	LRX_DATA_ENCODER_STATUS1_ADDR   0x400087;
#define	LRX_SHIFT_SEL_ADDR   0x400033;
#define	LRX_TEST_REG_ADDR   0x400010;
#define	LRX_L1_ROUT_COUNT_ADDR   0x400031;
#define	LRX_DATA_DELAY_ADDR   0x400004;
#define	LRX_L1_MEM_END_ADDR   0x40007f;
#define	LRX_L1_MEM_POINT_ADDR   0x400030;
#define	LRX_FLUSH_ADDR   0x40000f;
#define	LRX_RESET_ADDR   0x40000d;
#define	LRX_COLUM_MASK_ADDR   0x40000c;
#define	LRX_DATA_ENCODER_STATUS4_ADDR   0x40008A;
#define	LRX_ERROR_FORMAT_ADDR   0x400019;
#define	LRX_EVENT_END_ADDR   0x40005f;
#define	LRX_TEST_STIM_ADDR   0x400011;
#define	LRX_CLK_DELAY_ADDR   0x400003;
#define	LRX_DATA_ENCODER_STATUS5_ADDR   0x40008B;
#define	LRX_RX_ERROR_COUNT   0x400014;
#define	LRX_HIST_ADDR   0x400013;
#define	LRX_DATA_ENCODER_STATUS2_ADDR   0x400088;
#define	LRX_FIFO_EVDATA_STATUS_ADDR   0x400085;
#define	LRX_INPUT_STAGE_STATUS1_ADDR   0x400082;
#define	LRX_ENABLE_MCM_STIMULI_DATA   0x400016;
#define	LRX_DPM_BASE_ADDR   0x0;

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Define Documentation

#define CNTR_REG_ADDR   0x02;

#define DIG_PILOT_RESET_ADDR   0xE0;

#define DPM_FIFO_END_ADDR   0x22;

#define DPM_FIFO_START_ADDR   0x11;

#define EXTRA_HEADER_FIFO_ADDR   0x2E;

#define FED_DL_STATUS_WORD_ADDR   0x07;

#define FLUSH_DPM_ADDR   0x12;

#define FO_COINCEDENCE_COUNT_ADDR   0x6D;

#define FO_FROM_VME_ADDR   0x7f;

#define FO_GLOBAL_COUNT_ADDR   0x6C;

#define FO_TIME_COUNT_ADDR   0x71;

#define IRQ_PUSH_BUTTON_ADDR   0x2A;

#define J_PLAYER_ADDR   0x15;

#define LRX_BUSY_CONTROL_ADDR   0x400032;

#define LRX_BUSY_MASK_ADDR   0x400012;

#define LRX_CLK_DELAY_ADDR   0x400003;

#define LRX_CNTR_REG_ADDR   0x400000;

#define LRX_COLUM_MASK_ADDR   0x40000c;

#define LRX_DATA_DELAY_ADDR   0x400004;

#define LRX_DATA_ENCODER_STATUS0_ADDR   0x400086;

#define LRX_DATA_ENCODER_STATUS1_ADDR   0x400087;

#define LRX_DATA_ENCODER_STATUS2_ADDR   0x400088;

#define LRX_DATA_ENCODER_STATUS3_ADDR   0x400089;

#define LRX_DATA_ENCODER_STATUS4_ADDR   0x40008A;

#define LRX_DATA_ENCODER_STATUS5_ADDR   0x40008B;

#define LRX_DATA_ENCODER_STATUS6_ADDR   0x40008C;

#define LRX_DATA_ENCODER_STATUS7_ADDR   0x40008D;

#define LRX_DPM_ADDR_COUNT_ADDR   0x40000b;

#define LRX_DPM_BASE_ADDR   0x0;

#define LRX_EN_MOVE_BIT_ADDR   0x400034;

#define LRX_ENABLE_MCM_STIMULI_DATA   0x400016;

#define LRX_ERROR_FORMAT_ADDR   0x400019;

#define LRX_EV_DESCR_RAM_STATUS_ADDR   0x400083;

#define LRX_EVENT_END_ADDR   0x40005f;

#define LRX_EVENT_START_ADDR   0x400040;

#define LRX_FIFO_EVDATA_STATUS_ADDR   0x400085;

#define LRX_FIFO_PIX_DATA_STATUS_ADDR   0x400084;

#define LRX_FLUSH_ADDR   0x40000f;

#define LRX_HIST_ADDR   0x400013;

#define LRX_INPUT_STAGE_STATUS0_ADDR   0x400081;

#define LRX_INPUT_STAGE_STATUS1_ADDR   0x400082;

#define LRX_L1_MEM_END_ADDR   0x40007f;

#define LRX_L1_MEM_POINT_ADDR   0x400030;

#define LRX_L1_MEM_START_ADDR   0x400060;

#define LRX_L1_ROUT_COUNT_ADDR   0x400031;

#define LRX_MCM_STIMULI_DATA   0x400017;

#define LRX_RESET_ADDR   0x40000d;

#define LRX_RESET_SOFT_ADDR   0x40000e;

#define LRX_RX_ERROR_COUNT   0x400014;

#define LRX_SHIFT_SEL_ADDR   0x400033;

#define LRX_STATUS_REG_ADDR   0x400001;

#define LRX_TEMP_ADDR   0x400002;

#define LRX_TEST_REG_ADDR   0x400010;

#define LRX_TEST_STIM_ADDR   0x400011;

#define RD_FO_NUMBADDR   0x14;

#define RD_HISTOGRAM_ADDR   0x0d;

#define RD_L0ID_ADDR   0x2B;

#define RD_L1_ID_ADDR   0x13;

#define RD_L2A_ID_ADDR   0x2C;

#define RD_LENGHT_OF_BLOCK_ADDR   0x0b;

#define RD_START_ADDR   0x0a;

#define RESET_BCNT_ADDR   0x2D;

#define RESET_DETECTOR_ADDR   0x09;

#define RESET_EXTRA_HEADER_FIFO_ADDR   0x2F;

#define RESET_LINK_RX_ADDR   0x0f;

#define RESET_PIXEL_ADDR   0xE2;

#define RESET_TEMP_LIMIT_ADDR   0x76;

#define RESET_TTCRX_ADDR   0x0e;

#define RT_FPGA_VERSION   0x01;

#define SEND_TRIGG_SEQ_ADDR   0x10;

#define STATUS_REG1_ADDR   0x03;

#define STATUS_REG2_ADDR   0x04;

#define STATUS_REG3_ADDR   0x05;

#define VME_RESET_ADDR   0x23;

#define WT_HISTOGRAM_ADDR   0x0c;

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