Latest firmware versions

• Processing FPGA

Version number	0x20B
Last update of VHDL source	23 Apr 2009
Programming (.bit) file generation	17 Jun 2009
Last modifications	Implemented unique table of parameters for the fastor logic block; modifed fastor_logic.vhd and processing_registers.vhd
Xilinx Project location	pcphed08 E:\gaglieri_local\work\electronic_projects\pixel_trigger\proc_fpga_firmware
Xilinx project archive	https://edms.cern.ch/nav/CERN-0000006814/CERN-0000076367

Control FPGA

Processing FPGA

Functionalities to implement

• (DONE) Processing FPGA registers block
• (DONE) Processing FPGA counters for Fast-OR lines self testing
• (DONE) Registers in the CONTROL FPGA
  • (DONE) registers for the OPTIN fpgas programming "DONE" signals
  • (DONE) status of QPLL and TTCrx chips

• Parity checking functionality completion and verification
  • (DONE) Processing FPGFA
  • (DONE) OPTIN FPGA
• Counters start/stop commands
  • (DONE) in the PROCESSING
  • (DONE) in the OPTIN
• TTCrx and QPLL
  • (DONE) reset command, solve the problem of clock stability after receiving the TTCinit command
• (TO TEST) Setting the delay register of the TTCrx by I2C interface

• Timestamping
  • (DONE) in the OPTIN
  • (TO DO) in the PROCESSING

• (TO DO) Command to reset the OPTIN boards settings

• (DONE) Fast-OR processing block in Processing FPGA
  • (TO TEST) Coincidence logic between top outer, top inner, bottom inner, bottom outer layer for cosmics
  • (TO DO) Multiplicity algorithms

• (DONE) Main output block with compliance to CTP requirements (normal, random, signature, toggling)

• Trigger outputs
  • (DONE) Masking
  • (TO TEST) Dynamic programmability of output number 9
  • (TO DO) Optional self masking of the output during the chip readout
  • (TO DO) Function for the (optional) time extension of the Fast-OR pulse length to fix timing problems

• (TO DO) Remote reconfiguration of Processing FPGA

Problems, bugs to fix, other things to implement

* Communication bus

• • Bus turnaround state
    • (DONE) Processing FPGA code
    • (DONE) OPTIN FPGA code
    • (DONE) FIFO implementation for memory access in processing FPGA
    • (DONE) Correct target state machine for reading block phase
  • (DONE) Problem with parity checking when reading blocks of length 2 from OPTIN boards
  • (TO DO) Propagation delay from clock to irdy_i signal in control FPGA to be reduced, rewrite bus_master state machine with different syntax

• (DONE) Eliminate pad to pad path in processing FPGFA, time constraints failing

• (DONE) Timing refinement: add 1 ns to the processing DCM phase delay to center the processing FPGA clock phase wrt the OTPIN boards clock phases

• (TO DO) Counter of the output is not masked when the output is masked

• (TO DO) Implement the delay function in the extractor by RAM based fifo instead of dedicated registers

• Add timeout protection in all self-pointing states
  • (TO DO) Processing FPGA
  • (TO DO) OPTIN FPGA