Pixel Trigger components and construction
The Pixel Trigger project is in place to build an electronic hardware/software system linked to the ALICE Silicon Pixel detector (SPD). The Pixel Trigger system allows to process the low latency and low granularity Fast-OR signals of the SPD detector in order to generate an input for the ALICE Central Trigger Processor,within a latency of 800 ns. The result of the Pixel Trigger algorithm is taken into account in the ALICE Level 0 trigger decision.
- PitProgress page containing a summary of deliverables and ongoing activities
- PitHardware page containing information on the Pixel Trigger hardware activities
- PitPvss page containing information on the PVSS project controlling the pixel trigger system
- PitDriver page containing information on the Pixel Trigger driver software development
- PitFirmware with working info on the pit FPGA firmware development
- RouterDDL page containing firmware revisions for the implementation of the basic PIT DDL functionalities on the router card. Used only for driver development
For a list of Articles on the Pixel Trigger refer to the Publications.
2005 - Internal Note "Minimum bias triggers in proton-proton collisions with the VZERO and Silicon Pixel Detectors" [pdf]
2005 - Progress Report - J.Conrad [pdf]
2006 - LECC06 presentation "The Level 0 Pixel Triger System for the ALICE experiment" [pdf]
2008 - TWEPP08 presentation "The Level 0 Pixel Trigger System for the ALICE experiment: implementation, testing and commissioning" [pdf]