Links:
Pit FED's server prelimirary manual (pdf)
PIT FED server doxygen documentation (html)
PIT Database configuration library doxygen documentation (html)
PIT configuration database schema
The SPD and the Fast-OR
The ALICE Silicon Pixel Detector (SPD) comprises the two innermost layers of the ALICE Inner Tracker System (ITS). The SPD includes 120 detector modules each consisting of 10 pixel chips, each one of these is capable of generating a Fast-OR signal indicating the presence of at least one pixel hit in the corresponding 8192 pixel matrix. The ALICE Level 0 Pixel Trigger System extracts them, processes them and delivers an input signal to the Central Trigger Processor for the first level trigger decision within a latency of 800 ns.
The PIT Control system
The pixel trigger control system is a distributed system composed by 2 machines, one running PVSS acting as the supervision layer and another one running the PIT FED server acting as the driver layer of the system:
The PIT supervision layer
Based in CERN standard CERN’s standard SCADA (Supervisory Control and Data Acquisition) PVSS . It controls the overall trigger status taking appropriate corrective actions to maintain the system stability and ensuring the trigger quality.
The PIT driver layer
The PIT FED (Front End Device) Server acts as the driver layer of the system. Its communicates with the hardware through the ALICE standard Digital Data Link (DDL), publishes status and receives commands from other computers in the network using CERN standard Distributed Information Management System (DIM).
The PIT Control System Interconnections
The Pixel Trigger Control system was integrated as part of the ALICE Detector Control System (DCS). It the has to interface with several other ALICE sub-systems:
- the SPD DCS with which exchanges data during calibration scans,
- the CTP from which it receives configuration commands
- the Alice Experimental Control System (ECS) to whom it sends status information.
Pixel Trigger outputs and algorithms
Two versions of PIT processing firmwares are available since Jan 2013. See Firmware 1 and Firmware 2 below.
Pixel Trigger Firmware 1
PIT output number |
Trigger label |
Description |
Trigger logic |
0 | 0SMB | Minimum bias trigger | Ntot >= total threshold AND Nin >= inner threshold AND Nout >= outer threshold |
1 | 0SH1 | High multiplicity | Nin >= inner threshold AND Nout >= outer threshold |
2 | 0SH2 | High multiplicity | Nin >= inner threshold AND Nout >= outer threshold |
3 | 0SH3 | High multiplicity | Nin >= inner threshold AND Nout >= outer threshold |
4 | 0SH4 | High multiplicity | Nin >= inner threshold AND Nout >= outer threshold |
5 | 0SPF | Past future protection | Ntot >= total threshold AND Nin >= inner threshold AND Nout >= outer threshold |
6 | 0SX1 | Spare background | Nin >= Nout + background offset inner layer |
7 | 0SX2 | Spare background | Nout >= Nin + background offset outer layer |
8 | 0SBK | Background | Ntot >= background threshold both layers |
9 | 0SCO | Programmable cosmic algorithm | PROGRAMMABLE |
Algorithm selection |
Parameter number |
PIT output it applies |
Parameter name |
Default value |
Minimum value |
Maximum value |
0 | 0 | 0 | Total threshold | 1 | 0 | 1200 |
0 | 1 | 0 | Inner threshold | 1 | 0 | 400 |
0 | 2 | 0 | Outer threshold | 1 | 0 | 800 |
1 | 1 | 1 | Inner threshold | 1 | 0 | 400 |
1 | 2 | 1 | Outer threshold | 1 | 0 | 800 |
2 | 1 | 2 | Inner threshold | 1 | 0 | 400 |
2 | 2 | 2 | Outer threshold | 1 | 0 | 800 |
3 | 1 | 3 | Inner threshold | 1 | 0 | 400 |
3 | 2 | 3 | Outer threshold | 1 | 0 | 800 |
4 | 1 | 4 | Inner threshold | 1 | 0 | 400 |
4 | 2 | 4 | Outer threshold | 1 | 0 | 800 |
5 | 0 | 5 | Total threshold | 1 | 0 | 1200 |
5 | 1 | 5 | Inner threshold | 1 | 0 | 400 |
5 | 2 | 5 | Outer threshold | 1 | 0 | 800 |
6 | 0 | 8 | Background threshold both | 1 | 0 | 1200 |
6 | 1 | 6 | Background offset inner | 1 | 0 | 400 |
6 | 2 | 7 | Background offset outer | 1 | 0 | 800 |
9 | 0 | 9 | Cosmic algorithm selector | 0 | 0 | 5 |
Algorithm selector |
Algorithm logic |
0 | Coincidence top outer && bottom outer |
1 | Coincidence inner layer && outer layer |
2 | >= 2 Fast-Or in the inner layer && >= 2 Fast-Or in the outer layer |
3 | Coincidence top outer && top inner && bottom outer && bottom inner |
4 | Coincidence top outer && bottom outer && inner layer |
5 | Global OR |
Pixel Trigger Firmware 2
PIT output number |
Trigger label |
Description |
Trigger logic |
0 | 0SMB | Minimum bias trigger | Ntot >= total threshold AND Nin >= inner threshold AND Nout >= outer threshold |
1 | 0SH1 | High multiplicity | Nin >= inner threshold AND Nout >= outer threshold |
2 | 0SH2 | High multiplicity | Nin >= inner threshold AND Nout >= outer threshold |
3 | 0SH3 | High multiplicity | Nin >= inner threshold AND Nout >= outer threshold |
4 | 0SH4 | High multiplicity | Nin >= inner threshold AND Nout >= outer threshold |
5 | 0STP |
Topological trigger for ultra peripheral collisions |
Presence of at least two back-to-back pairs of hits in the phi plane (z projection), each pari with one hit in the inner and one in the outer layer |
6 | 0SLT | Multiplicity threshold, less than logic | Nin <= inner threshold AND Nout <= outer threshold |
7 | 0SX2 | Spare background | Nout >= Nin + background offset outer layer |
8 | 0SBK | Background | Ntot >= background threshold both layers |
9 | 0SCO | Programmable cosmic algorithm | PROGRAMMABLE |
Algorithm selection |
Parameter number |
PIT output it applies |
Parameter name |
Default value |
Minimum value |
Maximum value |
0 | 0 | 0 | Total threshold | 1 | 0 | 1200 |
0 | 1 | 0 | Inner threshold | 1 | 0 | 400 |
0 | 2 | 0 | Outer threshold | 1 | 0 | 800 |
1 | 1 | 1 | Inner threshold | 1 | 0 | 400 |
1 | 2 | 1 | Outer threshold | 1 | 0 | 800 |
2 | 1 | 2 | Inner threshold | 1 | 0 | 400 |
2 | 2 | 2 | Outer threshold | 1 | 0 | 800 |
3 | 1 | 3 | Inner threshold | 1 | 0 | 400 |
3 | 2 | 3 | Outer threshold | 1 | 0 | 800 |
4 | 1 | 4 | Inner threshold | 1 | 0 | 400 |
4 | 2 | 4 | Outer threshold | 1 | 0 | 800 |
5 | 1 | 6 | Inner threshold | 1 | 0 | 400 |
5 | 2 | 6 | Outer threshold | 1 | 0 | 800 |
6 | 0 | 8 | Background threshold both | 1 | 0 | 1200 |
6 | 2 | 7 | Background offset outer | 1 | 0 | 800 |
9 | 0 | 9 | Cosmic algorithm selector | 0 | 0 | 5 |
Algorithm selector |
Algorithm logic |
0 | Coincidence top outer && bottom outer |
1 | Coincidence inner layer && outer layer |
2 | >= 2 Fast-Or in the inner layer && >= 2 Fast-Or in the outer layer |
3 | Coincidence top outer && top inner && bottom outer && bottom inner |
4 | Coincidence top outer && bottom outer && inner layer |
5 | Global OR |