The Interlock System
Note: the interlock to the CAEN modules is provided via the Interlock FanIn board (aka Mike board) combining the Router interlock outputs wiht the interlocks from the cooling system and the interlock from the data acquisition box. A schematic of the interlock logic is here.
Configuration
Router number + FED: 4A
FSM: 4C
Test setup
Ch.0 - HS 159R
6 chips in the JTAG chain
DacRefHi = 106; DacRefMid = 95; GtlRefA = 148; AnTestHi = 70; AnTestLow = 147
VIPREAMP = 180; preVth = 190
Ch.1 - HS 170R
DacRefHi = 103; DacRefMid = 100; GtlRefA = 147; AnTestHi = 54; AnTestLow = 147
VIPREAMP = 160; preVth = 195 (200 also possible, except chip 3)
Ch.2 -
Ch.3 - HS 016R
DacRefHi = 127; DacRefMid = 134; GtlRefA = 150; AnTestHi = 68; AnTestLow = 152
VIPREAMP = 160; preVth = 200 (chips 2-4-9 = 195)
Ch.4 - HS 018L
DacRefHi = 60; DacRefMid = 57; GtlRefA = 150; AnTestHi = 80; AnTestLow = 40
VIPREAMP = 160; preVth = 180
Ch.5 - HS 025R
DacRefHi = 55; DacRefMid = 57; GtlRefA = 150; AnTestHi = 5; AnTestLow = 83
VIPREAMP = 180; preVth = 190
Delay = 54/192 for "Send trigger panel" (strobe length = 2)
Delay = 34/192 for CTP emulator
Some Router settings.....
- Delay TP-L1 = 104
- SEB/MEB option = 3
- L1 fine delay = 2 (set internal register 13 from Panel for experts -> General register access)
- Delay L0-L1 = 224