Dsf Log

16, 17 Apr 2008

Continued the optimization of Fast-OR DACs settings for two of the half staves installed and that can be used.

Set-up summary:

Detector

HS009 Connected to router 1, Ch 1 (one). Powered by caen module, MCM bias connected to output 0 (yes, zero) and BUS bias to output 1 (channels 39 and 40 in the CAEN view)

HS025 Connected to router 1, Ch 4. Powered by caen module, MCM bias connected to output 7 and BUS bias to output 8 (channels 47 and 48 in the CAEN view)

Two routers are installed and configured as router 0 and 1. Router 0 has first two link receivers from an old board version. Their clock/serial outputs are out of sync with the other 4 link Rx in the system. This router was not included in the readout. Router firmware version 24, link receiver 22a ("1022").

Pixel Trigger System

BRAIN board version 2 and 3 OPTIN boards plugged on it. Firmware was the latest up to date. One other OPTIN board was used stand alone with its patch board in order to sample Fast-OR and MCM feedbcak signals during the calibration of the Fast-OR DACs.

Software

fedServer was a modified version of what had been copied from point 2. It included Cesar's code for the storage and reterieval of detector configuration in the database. Various corrections and bug fixes have been applied by Cesar on this code during week 15. The server is stored on spdFed0 in folder C:\DCSSoftware\SpdFedServerP2Test\SPD_FEDServer_080415.exe

Activity

Several hours spent in learning on the Fast-OR optimization.

Worthwhile mentioning two things:

• The tuning has to be done with the HV set to have the detector fully depleted. We found that the Fast-OR noise behavior was changing when the Detector Bias voltage was increased.
• During the Fast-OR calibration procedure we used to send 1000 test pulses to the modules and counted the Fast-OR pulses returned by each chip. The procedure included switching on test pulses on the following pixels one by one (row, column): (0,0), (255,0), (255,31), (0,31), (100,16). The Fast-OR pulses returned were counted. On top we were measuring on the scope the duration of the Fast-OR pulse activation (if longer than 100 ns a double pulse is returned by the MCM feedback) and the timing with respect to the leading edge of the TEST_PULSE* signal sampled on the bus (Fast-OR pulses on edge rows showed different timing or even clock phase jittering).

Timing (latency) of the Fast-OR pulses is easily tuned by the

preVTH

dac.

For the two half staves considered, a common set of typical Fast-OR DAC settings was found:

FAST_CGPOL = 128, FAST_COMPREF = 128, FAST_FOPOL=0, FAST_CONVPOL=140.

On top we set: pre_VIPREAMP = 160.

Thresholds had to be tuned chip by chip for noise suppression and Fast-OR optimization. Following values were used. Chip number is the PVSS (i.e. spdFedServer) numbering which is reversed wrt DAQ numbering.

• preVTH in HS009: Chip0=180 , Chip1=175, Chip2=180, Chip3=170, Chip4=180, Chip5= 170, Chip6=190, Chip7=190, Chip8=180, Chip9=190
• preVTH in HS025: All chips 190

The HS009 had three chips with noisy Fast-OR outputs. This was cured by masking entirely chip 6 and 7 (DCS numbering) and masking all lines from 50 to 64 on chip 8.

The HS025 has one of the two sensors with no bias.

We manually positioned the half staves such to overlap as much as possible the active regions of the half staves.

Overall latency between the TEST_PULSE* on the bus and the Pixel Trigger system output obtained by the two half staves in coincidence was maesured: 733 ns. Total fiber length between SPD pp (i.e. edge of the pigtail) to pit front panel (i.e. LC input to the LC/MPT fan-in cable) was 34.5 m. More delay due to 1 m fiber + 6 m of LVDS cable from PIT to CTP has to be added to compare with ALICE setup. This means to add 35 ns to the previous, for a total latency of 768 ns expected in ALICE.

• Measurement of the Pixel Trigger latency. Top trace is TEST_PULSE* on the bus, bottom one is the Fast-OR coincidence between two half staves at the main output of the pit:

Cosmic ray coincidence run 4591 (aldaqpc018), using the pixeltrigger as trigger source and putting the half staves in coincidence. Run started at 10:57 and stopped at 16:06. Recorded 460 events. Of these there were 0 with no clusters, 8 events have clusters only on inner layer (HS009), 9 events have clusters only on outer layer. 17/460 = 3.6% of events unexpected. This could be traced to unoptimal strobing, due to the asynchronous setup randomly distributed cosmic rays.

09 Apr 2008

Reactivating the system for latency measurements

• Remarks on software
• If one clicks on "Read" of the MCM DPI straight after a HS Autoconfig command, the FED crashes (NOT systematic)
• If one first "Write" to the MCM DPI, then the reading is operational (some memory storage problem on Read??)
• If one clicks on "Read" on the Router Settings panel after "Auto Config" the spdFed crashes (NOT systematic)
• We observe that: when autoconfiguring the HS, the MCM is not busy. If we write to the DPI DACs, the MCM is busy if one does not set "Data_format_trig". If we check the "default" PVSS datapoints for that HS straight after the "Load configuration file" opertaion (with set to DP on), we see the value for Data_format_trig is 0. SO it seems that the value actually loaded in the HS is not retrievable by the panel for this DAC.
• The "Load Config File" panel cannot be open if the "Channels view" panel is alreay opened and viceversa. We notice that both panels show the same name on their top bar once they are opened. TO FIX
30 Jan 2008

Setting up the DAQ for the test half staves (formerly sector 0)

*Activate VISA driver

*Check for router temperature limits

Temperatures with fan, no water. HS_09 32.5 C HS_18 39.5 C HS_25 38 C

IV scans of HS09 and HS025 (file attached). HS018 cannot be biased with high voltage.

PT1000 measurements
HS4A
 Ohm C Status 5286 14.9 OFF 5682 35.4 ON 5681 35.4 ON

HS4C

 Ohm C Status 5284 14.8 OFF 5478 24.8 ON 5477 24.8 ON
I-V curves
Side A
 Ch0 Ch1 V Set V Read I(uA) V Set V Read I(uA) 10 10.5 1.28 10 10.05 1.280 20 20.05 1.150 20 20.05 1.16 30 30.1 1.5 30 30.1 1.53 40 40.15 2.65 40 40.15 2.65 50 50.2 4.69 50 50.2 4.68 60 60.2 7.61 60 60.2 7.59 70 70.25 11.5 70 70.250 11.38 - - - 80 80.250 16.02
Michael Burns: Cesar and I tried to do the test using my dummy sector but unfortunately we couldn't finish because the resistors were dissapating so much power that they unsoldered themselves so I have ordered some more powerfull ones so that we can carry with the test on Monday.

As a matter of interest we had everything seeming to be working with approx. 3.5 volts difference between the gnd of the PLC and the gnd of the half stave.

18 Oct 2006

Cesar measured the voltage between two negative(ground) inputs of the PLC module with the PT1000 chain, HS0 and HS1 with the following results

all off - 5,2 mv MCM only - 271 mv Bus + MCM - 655 mv

Cesar is going to repeat the test with a cable made by Mike to measure also between two different caen modules in the same module.
Measurement between two channels in two different CAEN modules,

HS0C and HS0A
100 mV -all OFF

176 mV - 0A(MCM only) 558.7 mV - 0A(MCM + BUS) 558.7 mV - 0A(MCM+BUS) 0C(MCM) 476 mV - 0A(MCM + BUS) 0C(MCM + BUS)

Min Tresh Hold Scan
 HS0, 1000 triggers HS1, 1000 triggers HS2, 1000 triggers HS3, 1000 triggers HS4, 1000 triggers HS5, 1000 triggers PVH Multiplicity PVH Multiplicity PVH Multiplicity PVH Multiplicity PVH Multiplicity PVH Multiplicity 200 0 200 0.008 200 0 200 0 200 0.0065 200 0 205 0 205 0 205 0 205 0 205 0.032 205 0 207 0 207 0 207 0 207 0 207 0.028 207 0 210 0.095 210 0.001 210 0.047 210 0.005 210 0.31 210 0.011 212 2.26 212 0.05 212 1.46 212 0.054 212 0.013 212 0.022 215 100.46 215 9.99 215 38.7 215 7.79 215 0.004 215 0.082
Automatic Mean-Tresh Hold scan Test

HS not turned on:

• Side A
• HV 4 goes in over current we cannot do the pixel config in the MCM
• Side C
• HV 1 and Hv 4 go in over current

Problem in the FED server: it is not setting the right values in the Anapil dacs Ivan, Ivan ...

Min Tresh Hold Scan HS 0 25m Cable

Misc_Control = 33 Delay_Control = 192

 PVH Hits Multiplicity Eficiency Pixel chips 190 0 0 0 - 200 0 0 0 - 207 0 0 0 - 208 0 0 0 - 209 0 0 0 - 210 14 0.148 0.883 pix5 211 53 0.564 0.946 pix5, pix6 212 328 3.489 1 pix2, pix4, pix5, pix6, pix7 213 880 9.362 1 pix2, pix4, pix5, pix6, pix7, pix9 214 3448 36.680 1 pix1, pix2, pix4, pix5, pix6, pix7, pix8, pix9 216 27244 289.830 1 pix0, pix1, pix2, pix4, pix5, pix6, pix7, pix8, pix9 219 112146 1232,37 1 pix0, pix1, pix2,pix3, pix4, pix5, pix6, pix7, pix8, pix9

23 Feb 2006

TOTAL POWER CUT in DSF on March 7 (8:00) till March 8 (13:00) due to work on the power connections for the CMS cleanroom.